Conventional SRAM cells use either six transistors (known as "6T SRAM") or four transistors and two resistors (known as "4T+2R SRAM"). The prior art 6T SRAM cell is schematically shown in FIG. 1. As seen, there are 6 MOS transistors in each cell. Two cross-coupled CMOS inverters (N1, P1 and N2, P2) are connected to two n-channel access transistors (N3 and N4). The SRAM cells are organized into an array in such a way such that the gates of access transistors in a row are connected to one word-line and the two drains of the access transistors are connected to a pair of bit lines (BL and BL-bar) in a column. Complementary data input is read or written through the column of BL and BL-bar and the word-line selects the specific cell to be written or read. The two cross-coupled inverters serve as a data latch to store data.
The prior art 4T+2R SRAM cell is shown in FIG. 2. This cell architecture uses polysilicon resistors as the load in each inverter (replacing the p-channel MOS transistors in the 6T SRAM cell). The 4T+2R SRAM cell is approximately 30 percent smaller than the 6T SRAM cell. This is accomplished by folding the polysilicon resistor on top of the n-channel MOS transistors in the inverter. The 4T+2R SRAM cell, however, is less stable than the 6T SRAM cell.
In each of the prior art SRAM cells in FIGS. 1 and 2, "local interconnects" must be used to connect the polysilicon gate of one inverter to the output of the other inverter. This adds additional manufacturing complexity and size to the SRAM cell.
What is needed is a SRAM cell that has a smaller size than that of the prior art.